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Methodology for System Partitioning of Chip-Level Multiprocessor Systems
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In today's market for integrated circuits, the product cycles require each stage of the design flow to be flawless to avoid costly redesigns and to not miss the product launch deadline. A decisive point is the determination of the appropriate architecture which affects the performance significantly. At a very early stage of the design flow, an evaluation of different implementation possibilities is very important to avoid wrong decisions which can challenge the outcome time-wise and budget-wise. In this book, constructive heursitics based on List Scheduling are developed for the HW/SW partitioning of process graphs which also permit the consideration of control dependencies necessary for the processing for the treatment of data communication protocols. Events which lie ahead in the schedule are considered during partitioning, since internal communication in complex architectures is increasingly recognized as a important factor for efficiency. Based on synthetically produced process graphs as well as a real-world application of data packet processing, the introduced algorithms are verified.
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