Estimation of Analog Layout Parasitics with Parameterized Polygons

Traditional analog integrated circuit design methodologies split circuit synthesis and physical layout design into different phases. Since analog circuits are usually very sensitive, physical layout effects, such as parasitics, can have significant influence on the performance and even the functionality of the design. Lack of considering layout effects in the circuit synthesis phase can result in numerous re-design iterations. Developing new analog design flows, methodologies, and automation tools are thus required in order to solve the problem. This book describes a new analog circuit design flow which uses parameterized representation of physical layouts in order to estimate layout-induced parasitics. With the use of algorithms for partitioning parameterized polygons, accurate models of extracted circuits, which include models of parasitics, can be generated automatically and efficiently. As a result, values of layout-induced parasitics can be calculated or estimated on the fly in the circuit synthesis process. Re-design iterations can thus be minimized.