Design of Low-Voltage CMOS Switched-Opamp Switched-Capacitor Systems

This volume emphasizes the design and development of advanced switched-opamp architectures and techniques for low-voltage low-power switched-capacitor systems. It presents a novel multi-phase switched-opamp technique together with new system architectures that are critical in improving significantly the performance of switched-capacitor systems at low supply voltages.Demand for low-power low-voltage integrated circuits (ICs) has rapidly grown due to the increasing importance of portable equipment in all market segments including telecommunications, computers, and consumer electronics. The need for low-voltage ICs is further motivated by CMOS technology scaling that requires low supply voltages for device reliability. On the other hand, switched-capacitor (SC) circuits, which have been well known for high accuracy and low distortion, have also become increasingly attractive for low-voltage, low-power, and even high-frequency applications. Switched-opamp (SO) technique has been proposed to enable SC circuits to operate with a single 1-V supply in standard CMOS processes without any clock voltage multiplier or low-threshold devices. However, the existing SO technique requires the opamps to turn off after their integrating phases and thus is not suitable for most of the switched-capacitor systems.§In Design of Low-Voltage CMOS Switched-Opamp Switched-Capacitor Systems, the emphasis is put on the design and development of advanced switched-opamp architectures and techniques for low-voltage low-power switched-capacitor (SC) systems. Specifically, the book presents a novel multi-phase switched-opamp technique together with new system architectures that are critical in improving significantly the performance of switched-capacitor systems at low supply voltages: A generic fast-settling double-sampling SC biquadratic filter architecture is proposed to achieve high-speed operation for SC circuits. A low-voltage double-sampling (DS) finite-gain-compensation (FGC) technique is employed to realize high-resolution SD modulator using only low-DC-gain opamps to maximize the speed and to reduce power dissipation. A family of novel power-efficient SC filters and SD modulators are built based on using only half-delay SC integrators. Single-opamp-based SC systems are designed for ultra-low-power applications. In addition, on the circuit level, a fast-switching methodology is proposed for the design of the switchable opamps to achieve switching frequency up to 50 MHz at 1V, which is improved by about ten times compared to the prior arts. §Finally, detailed design considerations, architecture choices, and circuit implementation of five chip prototypes are presented to illustrate potential applications of the proposed multi-phase switched-opamp technique to tackle with and to achieve different stringent design corners such as high-speed, high-integration-level and ultra-low-power consumption at supply voltages of 1V or lower in standard CMOS processes.