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Verification Methodology Manual for SystemVerilog

Language EnglishEnglish
Book Paperback
Book Verification Methodology Manual for SystemVerilog Hunter
Libristo code: 09165363
Publishers Springer-Verlag New York Inc., December 2014
Offers users the first resource guide that combines both the methodology and basics of SystemVerilog... Full description
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132.23 €
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Offers users the first resource guide that combines both the methodology and basics of SystemVerilog§§Addresses how all these pieces fit together and how they should be used to verify complex chips rapidly and thoroughly.§§Unique in its broad coverage of SystemVerilog, advanced functional verification, and the combination of the two.§

About the book

Full name Verification Methodology Manual for SystemVerilog
Author Hunter, Alan (North Carolina State University, University of Leeds North Carolina State Univ. North Carolina State Univ. North Carolina State Univ. No
Language English
Binding Book - Paperback
Date of issue 2014
Number of pages 503
EAN 9781461498131
ISBN 9781461498131
Libristo code 09165363
Publishers Springer-Verlag New York Inc.
Weight 795
Dimensions 155 x 28 x 29

Categories

Technology, Engineering, Agriculture > Electronics & communications engineering > Electronics engineering > Electronics: circuits & components
Technology, Engineering, Agriculture > Technology: general issues > Engineering: general
Technology, Engineering, Agriculture > Energy technology & engineering > Electrical engineering
Computing & Information Technology > Graphical & digital media applications > Computer-aided design (CAD)
Computing & Information Technology > Computer programming / software engineering > Compilers & interpreters
Computing & Information Technology > Computer programming / software engineering > Programming & scripting languages: general
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